Low Standby Power Consumption Techniques

The regulatory authorities have recognized that most power supplies operate most of the time under no-load standby conditions, so have introduced standards for standby as well as full load losses. This is because consumer electronics are so widespread that the average home has now upwards of 40 mains-powered devices in it which even in standby consume between 5%-10% of the total electricity demand.

The main energy efficiency regulations for external power supplies standby (no load) power consumption are:



External battery charger power supplies have stricter limits (0.075W up to 50W, 0.15W up to 250W) as it is assumed that they will be left plugged in yet spend most of their time in standby. Internal built-in power supplies have a more relaxed specification (0.5W in standby, 1W if there is an active display) as it assumed that the device will be switchedoff or disconnected if not needed.

The losses in an AC/DC converter which are not load-dependent can be split into passive and active elements:


There are several techniques that can be used to reduce the no-load or light-load power consumption.

Passive losses

HV start up disconnect

All AC/DC controllers need a start-up circuit. The rectified high voltage DC bus is fed via high resistance dropper resistors (usually two or more are used in series to spread the voltage stress across each resistor) and a Zener diode limiter to the Vcc input of the controller IC. Usually, as soon as the controller starts up, the operating Vcc current is then supplied by an auxiliary winding (which can also act as the feedback for primary side feedback applications). Thus, the HV start-up circuit must only provide enough current to start the controller IC oscillating: thereafter the “bootstrap” auxiliary winding takes over to provide the operating current (so called because of the image of pulling oneself up into the air by tugging on one’s own bootstraps or shoe-laces).

Figure 1 shows such an arrangement. R_HV1 and R_HV2 are the two high voltage dropper resistors wired in series to reduce the voltage stress across each resistor and ZD1 is the voltage limiting Zener diode (typically around 15V). After start-up, the operating current will be supplied by the auxiliary winding rectified by D1 and smoothed by C_Vcc. To avoid overloading the Zener diode, a series resistor R_supply limits the running current to a safe level.



Even if the majority of the operating current is provided by the auxiliary winding, significant current still flows through the HV start-up resistors after start-up (equal to the rectified DC mains voltage – ZD1 divided by R_HV1 + R_HV2). This represents a loss that becomes significant under no-load conditions. R_HV1 and R_HV2 cannot be reduced, otherwise the controller IC will either not have enough current to start up or the start-up time (time to fully charge up C_Vcc) would become unacceptably long.

One solution is to disconnect the HC start-up resistors immediately after a successful start-up by adding the components shown in blue in Fig 2:



During start-up, the base of Q1 is clamped at the Zener voltage, V_ZD1. The controller supply voltage, Vcc, is one base-emitter drop lower than this. Once the controller has started, the auxiliary winding increases the Vcc voltage until it is clamped to V_ZD1 + Vf_D1, or one diode drop above the V_ZD1 Zener voltage. This reverse bias turns off Q1, which was supplying the start-up current via R_HV3. The supply current for the controller is now supplied only from the auxiliary winding. The no-load residual current is now just the bias current flowing through R_HV1+R_HV2, but as this needs to be only just enough to turn on Q1 during start-up, it is much lower than the start-up current needed by the controller IC. A big advantage is that R_HV3 can now be made relatively low to give a high start-up current to give a fast turn-on time without affecting the HV dropper resistor loss after start up.

The beauty of this circuit is that it works with any topology or controller, analogue or digital. It also has the advantage that if the mains input voltage suffers a brown-out or black-out sufficiently long to stop the converter from running, that it auto-resets. There are controller ICs that incorporate such auto-disconnect circuits internally, but an external circuit allows more fine adjustment between stand-by power consumption and start-up time. The main disadvantages are that Q1 must be an expensive high voltage type and the residual losses due to the Zener bias current through R_HV1 and R_HV2.

Half-wave HV start up

A variation on the above circuit is to supply the HV start-up dropper resistor through separate diodes rather than the output of the bridge rectifier. This adds the cost of the additional diodes, but halves the voltage drop across the dropper resistor as the AC input is only half-wave rectified instead of being full-wave rectified. The big advantage is that the rectified HV voltage range between high-line voltage and the low-line is reduced, so in many cases, only one dropper resistor is needed instead of two, even for a wide range 100-240VAC input. The biggest disadvantage is that C_VCC must be made large enough to adequately smooth the half-wave rectified input at the low-line input voltage which can lead to a longer start-up time.

Bleeder Resistor Losses

External power supplies that are not permanently wired-in⁴ require a input discharge circuit to protect the user from a residual energy shock from the exposed connectors when the power supply is unplugged. The requirement is that the voltage stored in the input filter (mainly in the X-capacitor placed across the supply) should be reduced to a safe level (less than 60V) within 1 second of disconnection (IEC decision: CTL DSH 1080). Simply adding a bleed resistor, R_dis, across the input would meet this requirement (Figure 3), but at the cost of a significant no-load power consumption.



For a 230VAC/50Hz mains supply, a suitable fixed bleeder resistor would consume between 12mW and 20mW under no-load conditions, depending on the size of the X-capacitor required (the dropper resistor consumes VAC²/R).

Alternatively, there are several low power automatic X-capacitor discharge ICs that are available that monitor the zero-crossing of the input and then discharge the X-capacitor if the mains is disconnected:



C_t determines the delay time before the discharge is triggered, R1 and R2 limit the discharge current and provide additional surge protection for the IC. Such ICs typically consume only 1mW in standby.

Feedback Losses

The secondary side shunt regulator circuit is powered from the output capacitor. If an optocoupler is used, then the series regulator current limiting resistor, RLED, must be set high enough to drive the LED inside the optocoupler with enough current that the opto-transistor functions over the entire output voltage (including ripple) and operating temperature range. As the current transfer ratio decreases to as low as 50% at extremes of temperature, an adequate optocoupler current at lower or higher operating temperatures means at 20°C, the LED current must be double.



Pracical Tip: Under no-load, room temperature conditions, the largest power loss is usually the feedback circuit which can contribute 10-30mW to the overall power consumption! This is because a minimum current of 1mA is required for a 431 shunt regulator to maintain regulation and to supply its internal circuitry. However, to compensate for the opto-coupler performance deterioration over time and operating temperature, a minimum of 2mA must be set. For a 12V output, this current alone contributes 24mW on the output side or close to 30mW on the input side with efficiency losses.

On the primary side, the photo-transistor needs a pull-up resistor, R_opto, to ensure correct start up. This resistor cannot be made too large otherwise the feedback will become unstable or the optocoupler output will fall below the minimum compensation voltage that the controller can accept (Vcomp,min). Many controller ICs include an internal constant current source for the opto-coupler input which eliminates the need for an external R_opto pull-up resistor and reduces the stand-by power consumption. Equation 2 shows the calculation to determine the largest acceptable R_LED value:



CTR_min is the worst case current transfer ratio of the optocoupler over the entire operating temperature range and taking aging into account. A higher CTR will allow a higher value of RLED and a lower no-load power consumption.

An alternative solution is to use an active feedback regulator which avoids the minimum cathode current requirement of the 431 shunt regulator. The following example shows a current controlled feedback loop .



The output current is measured directly using the current shunt resistor R_shunt and then amplified By IC1. IC2 adds frequency compensation and supplies the drive current for the optocoupler LED. The advantage of this circuit is that either current or voltage can be used for the feedback control making a constant voltage or constant current power supply easy to implement. Also the gain (R1x/Rfx) can be optimized for the best optocoupler performance.

There is a further variation on this circuit where the optocoupler op-amp is replaced with a PWM generator. The PWM output can drive the optocoupler LED harder because as long as the mark/space ratio is below 50%, the average current is still low. The output is then integrated by C_comp to recover the original control signal.

The disadvantages of active feedback controllers are that they need a regulated supplies and reference voltages which also adds to the overall losses and the additional cost. For very low standby power consumption, primary-side regulation is usually needed to eliminate the losses in the shunt regulator and optocoupler.

Active losses

Active losses are characterised by a dependence on the switching frequency. Each time the transformer is energized or de-energized, losses occur in the switching or clamping circuits. To make the analysis easier, the commonly-used QR flyback topology is assumed.

Clamp losses

A passive snubber is designed to dissipate the excess energy stored in the leakage inductance of the transformer each time the main power switch is turned off. The power lost in the clamping circuit shown in Figure 4 is given in Equation 5, but it can also be rewritten as equation 3:



Where V_CL is the voltage across the clamp capacitor, f is the switching frequency and t_on, D is the turn-on time for the diode. The clamp losses can be decreased by reducing the voltage across the clamp capacitor (not very helpful as this increases the voltage stress on the switching transistor), by using a faster switching diode to reduce the t_on time or by reducing the switching frequency or load.

Variable switching frequency

Under full load a the converter will run at the minimum switching frequency determined by the input voltage and minimum off -time of the controller. As the load is reduced, the switching frequency will increase as I_peak reduces and the off time increases. The free-running QR switching frequency is given by equation 4 which is plotted in Fig 7:



Where V_DC is the rectified supply voltage, V_reflected is equal to V_out x turns ratio and C_oss is the switching transistor drain-source capacitance. For a fixed input and output voltage, the switching frequency is inversely proportional to the primary peak current which is load dependent.



The inverse relationship between switching frequency and load means that the power dissipation in the snubber remains constant from full load down to light load. This means that proportionally, the losses in the snubber become more significant as the load decreases. The switching losses are also frequency dependent; although the conduction losses decrease with load, the switching losses increase as the load decreases. The clamp and switching losses together mean that a power supply that operates very effi ciently at full load will become increasingly inefficient at loads below 50%. One solution to this problem is to introduce variable valley switching and pulse skipping under light load conditions.

Variable valley switching

Under light load conditions, the switching frequency will have reached its maximum. Any further reduction in load can only be accommodated by changing from CCM or CrCM mode to DCM mode. In effect, the controller does not switch on again after the first minimum (valley), but waits for the second, third, fourth, etc. valley before initiating the next switching cycle (fig. 8). The switching voltage increases slightly with each successive valley, but the stretched cycle time reduces the power consumption to give a net reduction in the losses.



As the transformer is fully de-energized at the start of the first valley, the output voltage must be maintained by the output capacitor until the next cycle. As the number of valleys increases, it becomes less important (and much more difficult to detect) the minima of the next valley, so the next cycle can be triggered even if the voltage is not a minimum. It becomes more im-portant to maintain the output voltage regulation than to minimise the switching losses by only switching at precisely the next valley.

Under no-load conditions, even this slowed-down, multiple valley switching cycle becomes wasteful of energy. There is a minimum on-time defined by the slew rate of the FET driver and the gate capacitance, so under no-load conditions the output capacitor may be overcharged. The output voltage rises and cannot be regulated back down.

Pulse skipping

No-load power consumption can be reduced using a technique called pulse skipping. Instead of a regular switching cycle, the converter generates a short burst of pulses and then idles to minimize the power dissipation and to keep the output voltage below the maximum limit. The short burst charges up the output capacitor to V_H and then the output voltage slowly decays until a lower threshold, V_L , is reached , whereupon the controller generates the next burst. The idle time is either fixed (the designer must choose the size of output capacitor to maintain the output between V_H and V_L) or can be made variable by changing a timer capacitor or by programming an internal register.



Using pulse skipping, the no-load power consumption can be reduced to below 100mW.The disadvantage of the pulse-skipping technique is a high output ripple and the difficulty of fil-tering out the bursts of high frequency operation on both the main input and on the auxiliary winding controller supply circuit.

Practical Tip: Use only a TVS snubber with pulse skipping controllers. A clamping capacitor would become completely discharged between bursts, so the magnetising energy in the transformer would be first diverted into the clamp capacitor before being transferred to the output. For the first few switching cycles in the bursts, the clamp dissipation would be disproportionately high compared to a low capacitance TVS snubber clamp. Additionally, the ESR of the output capacitor will affect the losses in burst mode. The increased ripple voltage is best accommodated by either a low ESR electrolytic or two electrolytics wired in parallel to reduce the overall ESR.

Synchronous rectification

The forward voltage drop across the secondary side rectification diodes generates a significant power loss, especially at lower output voltages. If a typical silicon rectification diode has a Vf of 600mV, then for a 3.3V output, then the rectifier diode dissipates 18% of the available output power. Replacing the output rectifier with a synchronous rectifier (SR) using MOSFETs reduces the power dissipation to approximately I_out² x R_{DS, ON}. (There are some additional MOSFET losses associated with the body diode conduction losses , gate drive dissipation and output capacitance losses, but these losses are small compared with the output current dissipation.)

For a typical power MOSFET with 2 mΩ R_DS,ON resistance, the power loss is only 20μW for a 100mA load current, compared to 60mW for the diode equivalent. So even for low output currents, SR can be a useful technique to reduce the low-load power consumption.

If the secondary winding output voltage is high enough and CCM or CrCM modes are used, then the MOSFETs can be self-driven. For low output voltages or DCM, the MOSFETs are not turned on fully for a large part of the switching waveform and the body diodes start to dissipate too much power. Figure 10 shows a typical cross-connected self-driven SR circuit.



The problem of low gate-source voltages can be overcome by adding an auxiliary secondary winding to drive the MOSFETs as in Figure 11.



Alternately, a secondary side SR controller can be used to drive the output MOSFETs. The synchronisation signals can be generated by monitoring the voltage across the MOSFET or, more accurately, generated by the primary side controller and transferred using digital isolators across the isolation barrier to synchronize the output rectifi cation with the primary switching controller. The use of a SR controller also allows precise control of the timing and deadtimes including a low-load mode with reduced blanking times.



Output Load detection (Zero-Power)

If an AC/DC power supply consumes 5mW or less under no-load conditions it is said to have zero standby power. This is extremely difficult to achieve as primary side regulation becomes unreliable as the output cannot be pre-loaded to keep the output voltage under control and the power consumption of a secondary side shunt regulator easily exceeds 5mW. If the PSR controller has a minimum switching frequency limit, then the dummy load can be replaced with a Zener diode to clamp the output voltage only when it rises too high. However, the output voltage tolerance must be very wide so that the Zener does not waste power during normal operation.

Zero-power operation is possible, however, by using an intelligent secondary wake controller paired with an intelligent primary side controller (fig. 10). The primary side controller IC contains a built-in start up circuit with disconnect function which can be directly driven from the rectified AC input. The auxiliary winding is used to subsequently power the IC and provide the signal for the primary side regulation (PSR). Over-current protection is provided by detecting the voltage across a shunt resistor connected in series with the MOSFET. Thus, during nor-mal operation, the controller maintains the output voltage within the usual regulation range like any other integrated flyback controller.

The difference is when the output load falls to zero (Fig 13).



Under no-load conditions, the controller goes into deep sleep mode and turns off the main power stage completely. The power consumption of the controller IC is now minimal and the output voltage is supplied only by the output capacitor, C_out.

If the output voltage drops below a certain limit, then the secondary side wake controller issues a short burst of short circuit pulses across the secondary winding which is detected on the primary side to wake up the PWM controller and initiate normal operation. The average power consumption of these short periods of activity interspersed with long sleep periods is below 5mW.

Measuring standby power consumption

It is not easy to measure the power consumption of an AC/DC converter in standby without the use of a power analyser. Especially for very low standby consumption designs ( < 100mW)an expensive high-end power analyser is required. The reasons for this are four-fold:

High sample rate: A high sample rate is needed to capture the short, high-frequency burst signals. It is not suffi cient to just detect the peak input current; the waveform must also be measured and analyzed. A sample rate of 20MHz is required to accurately measure a short current peak lasting only a few milliseconds.

High sensitivity: The peak input current of a low standby converter may be only 100-200μA. To get an acceptable measurement accuracy, a 1-2 μA current resolution is needed. Voltage resolution is not so critical (around 1V volt resolution is acceptable), but care must be taken when converting to true RMS values.

No auto-ranging: As most of the time, the power supply consumes very little power, any auto-ranging function will automatically select the highest possible resolution range. When a sudden burst signal occurs, the autoranging circuit may not react quickly enough. Therefore the autoranging function must be disabled.

Large memory: Due to the high sample rate and very long averaging time (minimum 500 mains cycles) , an analyser with a very deep memory is needed. Even with a high-end power analyser costing upwards of 30k€ , the no load power consumption can only be measured with a reliable accuracy of only around ±2%.

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4, Note: built-in power supplies or power supplies that are permanently connected to the mains supply do not need this protection circuit.