Power Factor Correction

PFC circuits also allow higher output powers without exceeding the maximum input current limit of the mains supply:



For an 85% efficient AC/DC converter operating from a fixed 230VAC supply fitted with a 10A over-current protection:
PF = 0.70 allows a maximum output power of 0.70 x 0.85 x 230V x 10A ≈ 1370W
PF = 0.95 allows a maximum output power of 0.95 x 0.85 x 230V x 10A ≈ 1860W

Passive PFC

Returning to our simple linear power supply design in Chapter 2, the reactive power is mainly capacitive although the load across the mains supply is the transformer, a primarily inductive component. This is because the transformer “reflects” the secondary load phase shift to the primary side. Thus the reactive power seen by the mains supply is mainly capacitive and the current leads the voltage. It would be possible to shift the current waveform to partially correct the power factor by adding a series inductor - but it is not possible to fill in all of the greyed-out areas in the waveform shown in figure 2.3 with current, so the power factor cannot be made perfectly equal to 1.

In practice, a passive power factor correction (PFC) solution can improve an uncorrected power factor from around 0.4 to around 0.7 by using PFC chokes (typically an iron-cored transformer with only a single winding) but such inductors are often nearly as large and as heavy as the isolation transformer itself:



One of the main problems with the simple passive PFC correction circuit shown above is that the PFC choke can only operate over a limited input voltage range and still adequately correct the power factor. A solution often used in very low-cost passive PFC circuits is to add a voltage selector switch between 115VAC and 230VAC operation (figure 7.2). The switch is either open (230V) and the PFC choke is connected in series with the full wave rectifier or closed (115V) making the circuit then the same as a half wave voltage doubler so that the output voltage stays the same (only the left half of the PFC choke and the left half of the full bridge are active).



The voltage doubler capacitors can be calculated from the relationship:



For a 100W power supply with 80% efficiency at 115VAC/60Hz input:
Iin 100W/325VDC= 0.3A/0.8=0.375A, tholdup = 1/120Hz =0.08

So, assuming an acceptable ripple Voltage of Vripple = 30V





Valley Fill PFC

Although the switched range passive PFC is very effective for high power (100W to 250W), with PFC values of >0.95 at 230VAC and >0.98 at 115VAC possible, it is not so effective at lower power levels. However, it is also possible to get >0.9 power factor at low power levels using only passive components.

The technique required is called “valley-fill” and relies on using steering diodes to charge up two output capacitors to half of the peak voltage. This means that they will start to draw input current much earlier in each mains half-cycle (at half the peak input voltage instead of nearly at peak input voltage) and continue to draw current until much later in the half-cycle (again until the voltage falls to half of the peak voltage). The disadvantage of this arrangement is a very high output ripple of 50% of the DC output voltage.





Valley-fill circuits are most commonly used in triac-dimmable LED drivers. Firstly, the valley-fill circuit also works well with a phase cut mains input consisting of short sections of the mains sinusoidal waveform and secondly, a high output ripple is not so important (the human eye is not very good at noticing LED flicker at frequencies of around 100Hz). Finally, it is a cost effective solution which is important for the cheaper end of the lighting market. However, for industrial-grade power factor corrected supplies, the high output ripple is often unacceptable. To get a good power factor with low output ripple, active PFC is required.


Acitve PFC

Active power factor correction uses a variable mark-space PWM control to manipulate the input current to force it to align with the input voltage. To do this, it is necessary to increase the voltage on the capacitor to ensure that at any point during the half-cycle, it can still be charged. Therefore all active PFC circuits are effectively DC boost converters. The boost voltage must be equal to or higher than the highest rectified input peak voltage, so typically 400V-425V is selected. Any higher and there will be unnecessary voltage stress on the boost capacitor and switching elements, any lower and the PFC circuit cannot ensure that the charging current can be controlled throughout the half-cycle.
There are four main topologies used for active power factor correction; discontinuous, continuous, critical-conduction and mixed-mode.

DCM power factor correction



The PFC controller alters the duty cycle during the rectified input half-sine wave so that the mark/space ratio is smallest at the peak of the input voltage and highest at the start and end of the cycle. The PWM frequency remains constant. The rectified input voltage is divided down by R1/R2 and used to synchronize the PFC controller. The output voltage is divided down by R3/R4 for the feedback loop that stabilizes the output voltage. The storage capacitor Cout is charged up to a much higher voltage than the peak input voltage through the action of the boost converter formed by L, Q1 and D5, but the charging current is a series of short pulses throughout the input half-cycle, longer at low input voltage and shorter at higher input voltage. The average current through the choke therefore follows the input waveform voltage so the power factor is very close to 1.



The inductor current is shown in black, the input voltage in red and the average input current in blue. The inductor current falls to zero at the end of each PWM pulse.

The main advantage of DCM power factor correction is that the inductor is fully magnetized and de-magnetized during each PWM cycle, so the inductor current falls to zero at the end of each pulse. The switching transistor then switches on at zero voltage/zero current, so it is very efficient and almost lossless. Also, the recovery speed of the boost rectification diode is not critical.

The disadvantage of this method is the high EMI generated from the high peak currents of the chopped input waveform. A discontinuous PFC circuit needs a very good input EMC input filter to meet the regulatory conducted interference limits. The PFC choke must also be capable of handling the high peak currents, so the choke is large and heavy.

CCM power factor correction

A solution to the EMC problems of DCM power factor correction is to use a continuous conduction power factor correction controller. This is the same circuit as above, but the inductance is increased so that the current in the choke varies only slightly above and below the ideal sinusoidal waveform. Typically, the CCM current ripple is chosen to be around 20%-40% of the average inductor current. Again, the PWM frequency is constant:



The inductor current is shown in black, the input voltage in red and the average input current in blue. The inductor current does not fall to zero at the end of each PWM pulse.

The PWM controller is more complex as it must track the input voltage and adjust the input current more precisely, but the EMI generated is much lower as the input current is continuous and not pulsating.

The major disadvantages are the significantly higher switching losses in the transistor and higher recovery losses in both the diode and the transistor. For a CCM design, the boost rectification diode must be ultra-fast (very low Qrr). The choke needs to have a much larger inductance than for a DCM design, although the peak current is lower.

CrCM power factor correction

Both the DCM and CCM power factor correction circuits use a fixed PWM frequency. However, if the frequency is also made variable and synchronized to the input half-cycle, then the inductor current can be adjusted so that it only just touches zero at the end of each PWM pulse, whatever the input voltage is during the half-cycle (this is called boundary conduction mode (BCM) or critical conduction mode(CrCM).



The inductor current is shown in black, the input voltage in red and the average input current in blue. The inductor current falls to zero at the end of each PWM pulse and the PWM frequency varies.

With CrCM control, the switching losses in the transistor and the recovery losses in the diode are as low as in the DCM circuit plus the inductor can be made smaller than in the CCM circuit because the peak currents are lower.

The disadvantage is the variable frequency PWM requires EMC filters that are effective over a wider range of frequencies.



All three solutions have the same average inductor current, but the peak-to-peak inductor current in the CrCM is a compromise between the very high levels of the DCM inductor and the very low levels of the CCM circuit.

Mixed-Mode PFC

There are many PFC controllers on the market that are capable of switching between different modes of operation according to the operating conditions of the converter. A chosen value of choke that works well with a CCM controller at low input voltage (90 – 125VAC) may transition to DCM due to the lower input current at higher input voltages (180-265VAC), thus harming the power factor correction figure. To avoid having to make a compromise, the controller can be made variable frequency/variable PWM to keep the circuit in CCM/CrCM throughout the input voltage range. There are also powder core chokes called “swinging chokes” that change their inductance according to the current though them. At low currents, the inductance increases, thus keeping the PFC in CCM/CrCM whatever the operating conditions.

Practical Tip: PFC stages are susceptible to damage from input surge voltages. The bridge rectifier will rectify both positive and negative-going surges into a high positive voltage into the PFC choke. The resulting high current can rapidly saturate the core so that the choke no longer behaves like an inductor, but lets all of the surge voltage through. The PFC diode now has to cope with the high charging current (sometimes hundreds of amps) into the PFC capacitor and can quickly fail. The solution is to add a high current diode in parallel with the PFC choke and diode. Under normal operating conditions, the PFC voltage will be higher than the input voltage and the bypass diode will be reverse biased. Under surge conditions, the input exceeds the PFC voltage and it will conduct, relieving the stress on both the PFC diode and PFC choke as well as reducing the voltage across the bridge rectifier.



Interleaved PFC

As has been mentioned several times in this chapter, the EMC considerations are an important factor in choosing the appropriate conduction mode for the PFC controller. If the EMI is too high to be effectively filtered out then an alternative topology is to use two interleaved PFC circuits so that the ripple current in each stage is halved and added in anti-phase.

Interleaving also has the advantage of sharing the output current across two inductors and two diodes, thus allowing either higher output currents or improved operating temperatures.



An interleaved PFC is mainly used for high power AC/DC converters where the high input current would make the EMC input filter very bulky and more expensive than the extra circuitry of using two CrCM PFC boost converters. The PWM outputs operate 180°C out of phase, so although the current in either of the inductors falls to zero at the end of each pulse, the current flowing into the PFC capacitor is continuous (current flows alternately through D1 and D2).

The output voltage ripple is significantly lower than is possible with a single stage PFC and with a 50% duty cycle, the interleaved topology has zero input current ripple as the two PFC stages cancel out. Besides the increased cost, the biggest disadvantage is that all of the components used must be very carefully matched to maintain the same performance over all operation conditions.



Bridgeless (totem pole) PFC

The bridgeless or totem-pole PFC topology is becoming more popular because of its very high efficiency. The bridge rectifier diodes are replaced by two high voltage transistors that alternately switch at the mains frequency to rectify the input. The diode forward voltage drops are therefore eliminated and the internal body diodes of the transistors aid the current flow and increase the efficiency.

It is usual to use different transistor types for the slower 50Hz switching and the high frequency PFC switching.



The single switching FET in the previous PFC designs is replaced by two FETs Q1 and Q2. During a positive mains half-cycle, Q4 is switched on, Q3 is off, Q1 is operated with a PWM signal to boost the output voltage and Q2 is operated with the inverted PWM signal to act as a rectifier. During a negative mains half-cycle, Q3 is switched on, Q4 is off, Q2 is operated with a PWM signal to boost the output voltage and Q1 is operated with the inverted PWM signal to act as a rectifier.

As Q3 and Q4 are switched at a low frequency (50/60Hz), they do not need to switch quickly and can be regular MOSFETS. Diodes are placed in parallel to help increase the efficiency by sharing the peak current, but the power switching is done with the MOSFETs. The forward voltage losses of the conventional bridge rectifier are thus eliminated, so the rectification losses can be very low (<1%).

The transistors Q1 and Q2 cannot be MOSFETs because the reverse recovery losses would be too high. The switching delay would cause shoot-through and large current spikes during AC zero-crossing. One solution is to use JFET transistor in a cascode configuration with a MOSFET:



The JFET is normally on and has a gate input that is effectively grounded. When the MOSFET is off, the MOSFET V_DS rises until the JFET V_GS is sufficiently negative to switch the JFET off. The supply voltage then appears almost entirely across the JFET. When the MOSFET is switched on, the V_DS drops to close to zero and the JFET turns on. The advantage of this arrangement is that the JFET gate and the MOSFET V_DS and V_GS are all close to zero, so the reverse recovery, Coss and Miller capacitance losses are also close to zero. The switching speed is vastly improved.
br> More recently, high electron mobility transistors (HEMT) such as GaN FETS are being used to replace the cascode as they are ideal for such totem-pole topologies (very fast switching slew rates, no body diode, and low gate capacitance). Overall PFC stage efficiencies in excess of 99% are possible with GaN FET totem pole designs.

The following bridgeless totem pole PFC circuit uses two half bridge power stages to replace the bridge rectifier and the PFC switcher normally required by AC powered applications. The synchronous rectifier consists of two silicon MOSFETs alternately switched with a 50% duty cycle at 50/60Hz in time with the AC mains input. This creates a rectified output without the need for an input bridge rectifier. The PFC half-bridge circuit runs with a higher frequency and variable duty cycle PWM signal to perform the power factor correction function using low loss GaN transistors. With the low component count, the gate driver components can be placed closer together and parasitic inductances and stray capacitances minimized. Two RP-1506S converters and a dual channel digital isolator are used to create the fully isolated high-speed half-bridge GaN gate driver circuit for the PFC with a BOM count of only 20 parts.

The 50/60Hz AC synchronous rectification half-bridge runs at a much lower frequency, so lower-cost MOSFETs can be used without sacrificing overall efficiency or performance. The isolated +15V high-side MOSFET gate drive power is supplied by a RP-1515S converter. All three DC/DC converters used offer 5.2kVDC isolation and <10pF isolation capacitance. The low-side MOSFET gate driver can be supplied directly from the 15V on-board power supply (no isolation is needed).



The disadvantages of the bridgeless PFC are the extra complexity (four isolated FET drivers are required), the accuracy of the timing needed (especially during mains zero-crossing, where it is important to introduce enough dead time to avoid shoot through, but not too much as this will harm efficiency) and the difficulty of synchronising the circuit to a noisy mains supply. In addition, the controller IC needs to have a current transformer or Hall Effect sensor to be able to monitor the bidirectional inductor current accurately enough to maintain a high efficiency over the entire load and supply voltage range.



This digital controller uses three control loops: a voltage control outer loop (using the V_dc input), a sine wave reference loop (synchronized to the V_ac input) and a current control inner loop (using the IL input) to maintain accurate regulation with a high power factor. Such control complexity means that only digital controllers are really suitable for this topology.

In addition, a data link to the digital LLC converter controller allows interactive operation to change the response characteristics according to load conditions.

One of the biggest disadvantages of totem-pole PFC stages is that the neutral connection is switched at 50/60Hz. This creates serious EMI issues, especially if the neutral is connected to ground in the switching cabinet. A solution to this problem is to use neutral point clamping (NPC), a variation on the multilevel-type topology.

Figure 18 shows a simplified NPC circuit. Transistors Q3 and Q4 switch at the mains frequency and Transistors Q1 and Q2 switch at the PFC frequency. Two PFC capacitors are used to hold the positive and negative rectified output, so the PFC bus voltage is double that of a standard totem-pole PFC stage. The neutral connection is unswitched and therefore stays quiet.

Figure 19 shows a further variation where the two diodes D1 and D2 are replaced by additional switching transistors. The advantage of this modification is not just lower overall losses but the possibility to use adaptive PWM control to balance out the stresses in both legs of the circuit.

The disadvantage of NPC is a more complex control scheme, higher voltage rated transistors and the need for isolated drivers, so this topology is mostly used for high power PFC stages, where the savings in the EMC input filter outweigh the additional costs.