Future-proofing Your Power Switching Solution
Mar 22, 2024
There is an increasing demand for higher efficiency at elevated power levels for automotive, industrial, and inverter-based applications. For electric vehicles (EVs), this boost in efficiency is essential for extending performance and range through more efficient motor drives and rapid battery chargers. For industry, energy efficiency is crucial for reducing global power consumption and supporting long-term sustainability, hence the rising interest in the efficiency benefits of DC microgrid technology. For green renewable energy, high efficiencies foster the uptake of photovoltaic, water, and wind generation, extracting the maximum energy from limited natural resources.
To achieve this critical goal, power electronics are transitioning to higher switching frequencies and increased voltages, while balancing cost-performance tradeoffs and reducing overall size (Figure 1).
However, such a transition necessitates the integration of advanced semiconductor devices, with new iterations of power MOSFETs and wide-band gap SiCs and GaNs being released regularly.
This poses a challenge for design engineers: in an environment marked by constant advancements in power switching transistor technology, how can one future-proof power switching stages take advantage of these new generations without the need for constant redesign?
Let us take a typical power design requirement as an example:
A solution is needed for an advanced three-phase battery charger for EVs with high conversion efficiency and compact design. The power stage should be fully bidirectional and equally efficient in both directions: from AC-to-DC and from DC-to-AC. The AC side should feature active power factor control (PFC), and the DC side should have low switching losses and interface with battery packs with voltages up to 800VDC. The design should operate at a high switching frequency to reduce the size and weight of the inductive components.
This poses a challenge for design engineers: in an environment marked by constant advancements in power switching transistor technology, how can one future-proof power switching stages take advantage of these new generations without the need for constant redesign?
Let us take a typical power design requirement as an example:
A solution is needed for an advanced three-phase battery charger for EVs with high conversion efficiency and compact design. The power stage should be fully bidirectional and equally efficient in both directions: from AC-to-DC and from DC-to-AC. The AC side should feature active power factor control (PFC), and the DC side should have low switching losses and interface with battery packs with voltages up to 800VDC. The design should operate at a high switching frequency to reduce the size and weight of the inductive components.
A possible solution incorporating a three-phase PFC, full-bridge bidirectional LLC, and active rectifier is shown in Figure 2. This solution requires fourteen power transistors, which for optimal cost vs. performance could be a mix of MOSFETs, SiC, and GaN transistors.
All the power transistors will need individual gate drivers, with the high-side transistors (Q1, Q3, Q5, Q7, Q9, Q11, and Q13) also needing galvanic isolation. If the gate drivers have separate Out+ and Out- pins, then different gate resistors for the on and off cycles can be used to optimize the switching characteristics.
Also, the isolated Vpos and Vneg voltages can be chosen to fully enhance the transistor during the on-cycle and rapidly discharge the gate capacitance during the off-cycle. A negative “off” voltage also makes the switching more reliable by eliminating false turn-on due to source inductances1. Therein lies the problem: different switching technologies and transistor generations have different recommended and absolute maximum gate drive levels (Figure 3).
All the power transistors will need individual gate drivers, with the high-side transistors (Q1, Q3, Q5, Q7, Q9, Q11, and Q13) also needing galvanic isolation. If the gate drivers have separate Out+ and Out- pins, then different gate resistors for the on and off cycles can be used to optimize the switching characteristics.
Also, the isolated Vpos and Vneg voltages can be chosen to fully enhance the transistor during the on-cycle and rapidly discharge the gate capacitance during the off-cycle. A negative “off” voltage also makes the switching more reliable by eliminating false turn-on due to source inductances1. Therein lies the problem: different switching technologies and transistor generations have different recommended and absolute maximum gate drive levels (Figure 3).
A gate driver design optimized for IGBTs with asymmetric supply voltages of +15/-9V would severely stress a first- or second-generation SiC with only 1V headroom to the negative absolute maximum limit and not work at all with a third-generation SiC transistor. A similar problem exists with a design that needs to transition from a first-generation SiC to a second- or third-generation SiC—the +20V positive rail would be the same as or exceed the absolute maximum limit of the newer generations, risking device failure.
The tendency is that each new generation of power transistor will be fully enhanced or fully depleted with lower gate drive voltage levels, but the optimal gate drive voltage levels will still vary between manufacturers, development iterations, and transistor types. As the isolated gate driver power supply voltage ((Vpos and Vneg) is provided by either an isolating transformer or an isolated DC/DC converter, different solutions will be required for each power transistor selection, even though the gate driver itself is usable for all transistor types. This means that even using a pin-compatible second-source switching transistor may require significant design changes in the isolated power supply.
What is needed is a programmable isolated asymmetric power supply to allow the gate driver circuit to be optimized for different transistor options, possibly including new generations that have not even been released yet.
The tendency is that each new generation of power transistor will be fully enhanced or fully depleted with lower gate drive voltage levels, but the optimal gate drive voltage levels will still vary between manufacturers, development iterations, and transistor types. As the isolated gate driver power supply voltage ((Vpos and Vneg) is provided by either an isolating transformer or an isolated DC/DC converter, different solutions will be required for each power transistor selection, even though the gate driver itself is usable for all transistor types. This means that even using a pin-compatible second-source switching transistor may require significant design changes in the isolated power supply.
What is needed is a programmable isolated asymmetric power supply to allow the gate driver circuit to be optimized for different transistor options, possibly including new generations that have not even been released yet.
RECOM has introduced the R24C2T25S DC/DC converter—an SMD device in a SOIC package with an integrated isolation transformer (Figure 4). The outputs can be independently set in the range between +2.5V to +22.5V and from -2.5V to -22.5V by changing resistor values in a feedback divider circuit, meaning that one power supply solution can provide +15/-9, +20/-5, +18/-4, +15/-3, or any other output voltage combination as long as the combined output lies in the range of 18 to 25V.
This allows the designer to switch easily between first and second-source power transistor suppliers by changing the BoM resistor values, but not the PCB design. It also means that if a completely new generation of power transistor is released with, say, +14.5/-3.5V optimal gate drive voltages, the solution is future-proofed. Finally, the output voltages are independently regulated, which is essential when driving the gate to voltages that are very close to the absolute maximum levels to get the highest possible switching efficiency. As power levels increase into the kilowatt range, the environment around the gate driver and gate driver power supply becomes harsher. Despite the low switching losses of advanced WBG power transistor technologies, high ambient operating temperatures are to be expected. Hard-switching topologies and demanding thermal cycles may affect power supply lifetime and performance.
The R24C2T25S is designed with these challenges in mind, offering robust thermal performance, wide temperature range support, and low EMI emissions, making it suitable for the next generation of power switching solutions.
This allows the designer to switch easily between first and second-source power transistor suppliers by changing the BoM resistor values, but not the PCB design. It also means that if a completely new generation of power transistor is released with, say, +14.5/-3.5V optimal gate drive voltages, the solution is future-proofed. Finally, the output voltages are independently regulated, which is essential when driving the gate to voltages that are very close to the absolute maximum levels to get the highest possible switching efficiency. As power levels increase into the kilowatt range, the environment around the gate driver and gate driver power supply becomes harsher. Despite the low switching losses of advanced WBG power transistor technologies, high ambient operating temperatures are to be expected. Hard-switching topologies and demanding thermal cycles may affect power supply lifetime and performance.
The R24C2T25S is designed with these challenges in mind, offering robust thermal performance, wide temperature range support, and low EMI emissions, making it suitable for the next generation of power switching solutions.
1For a detailed analysis of the need for a negative gate drive voltage (also for low side switchers) refer to the whitepaper “ Designing Robust Transistor Circuits with IGBTs, SIC MOSFETS”.
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