DC/DC Converters for GaN Gate Drivers

Feb 5, 2019
This whitepaper shows how the usage of DC/DC converters with low leakage capacitance and compliance with design guidelines eliminate these causes of failure and simplify the design.

1. GaN Gate Drive Considerations - lntroduction

Gallium Nitride (GaN) semiconductors are High Electron Mobility Transistor (HEMT) devices, a class of transistors with almost perfect switching characteristics. HEMT means that electrons travel within the internal crystal structure as a two dimensional electron gas with very high mobility, thus creating a device with very high conductivity and low RSDON. The use of GaN chemistry increases the breakdown voltage which means that the layers within the transistor can be made very thin and close together. This both accelerates the switching speed and reduces the gate capacitance.
The enhancement mode type (E-HEMT) has a depletion zone under the gate which blocks the flow of electrons and requires a positive gate voltage with respect to the source pin to turn on.

As the depletion zone under the gate is so thin, very little injected charge is needed to turn the transistor on and off, so switching speeds in the MHz region are possible without incurring high switching lasses.


Fig. 1: Diagrammatic layout of an Enhancement Mode GaN Transistor in the OFF and ON conditions
The extreme thinness of the gate isolation layer means that high gate-source voltages will cause an internal flashover, even though the material itself has a high breakdown voltage rating. A GaN E-HEMT has a typical full enhancement voltage of 7V but will be damaged if the VGS exceeds ±1OV, much lower than the gate voltages that are typically used in IGBT or SiC gate drivers. Due to the extremely fast rise and fall times of the low-capacitance gate channel, any excessive inductance in the external gate drive could cause spikes or voltage ringing and exceed these voltage limits. Therefore a 6V gate drive voltage is a good compromise between high efficiency and staying within a safe operating area.

IGBT or SiC gate drive circuits also typically turn off with a negative gate drive voltage. This speeds up the charge extraction from the gate capacitance and therefore the switch-off time. GaN Transistors have such low gate capacitance that a negative gate drive is not necessary. A gate voltage of OV will completely and reliably turn off the HEMT in nanoseconds. Only if the layout has excessive inductance would a negative gate drive offer protection against unintentional turn-an caused by ringing. However, as HEMT do not have a body diode like a MOSFETs and are symmetrically conductive devices, a negative gate voltage will increase reverse conduction lasses. A single ended 6V-OV gate drive voltage is ideal.

Figure 2 shows typical gate driver voltages that are commonly used. The 1st Generation SiC MOSFETS use +20/-5V supplies, but 2nd Generation devices will most likely use +15/-3V supply voltages:



Fig. 2: Typical Gate Driver supply voltages for IGBT, SiC and GaN drivers

2. GaN Gate Drive Considerations - Design Guidelines

1: The majority of ultrafast gate drivers ICs have an under-voltage lock-out (UVLO) function that disables the output if the supply voltage is too low. Those meant for IGBT/SiC applications will often have a relatively high UVLO level as they are designed to operate from supply voltages up to 24V. A gate driver that is compatible with the much lower gate voltages used in GaN must be selected.

2: The current needed to charge and discharge the gate capacitance is dependent on the gate capacitance and the rate of change of the gate voltage. Although the GaN gate capacitance is very low, the high dv/dt means that a gate driver with a current drive capability of at least ±0.5A (or better 1A sink) is required. This peak current will be supplied from a ceramic capacitor mounted as close to the driver pins as possible, so the average supply current will be much lower (in the tens of milliamps range). The gate driver sink drive should be low-impedance (<2 Ohms) to reduce the chance of cross-conduction (see next comment).
3: An ultrafast gate drive design is susceptible to undesired turn-an (cross-conduction) due to parasitic gate driver inductances interacting with the high Miller capacitance discharge current thus creating a ringing oscillation that could send the gate voltage momentarily high again. The slew rates can be limited by a dv/dt limiting resistor to reduce the possibility of this effect. A turn-an gate resistor in the range of 10-20 Ohms will typically give a 80-40kV/µs slew rate. The turn-oft resistance should be smaller to reduce the turn-oft lasses. A Schottky diode with a resistor in parallel with the gate resistor can be used to independently control the turn-an and turn-oft slew rates (Figure 3).

4: High side gate drivers are often implemented with a bottstrap power supply circuit (figure 4). Although this means that the same isolated power supply can be used for both high-side and low-side drivers, it has some inherent weaknesses.


Fig. 3: Slope control using gate resistors
The bottstrap diode must have an ultrafast revovery characteristic. If it cannot switch off as quickly as the GaN output then a reverse current will flow back into the VDD supply. Not only will these current spikes affect the lifetime of the diode, but the resulting high frequency interference on the supply rail will cause havoc with the EMC compliance.

The gate driver bootstrap supply voltage is dependent on the difference between the VDD supply and the capacitively-coupled output (witching node) voltage. This means that the voltage across the bootstrap capacitor can vary by more than ±20% during operation.

There will be a volt drop across the high voltage bootstrap diode of around 0.8-1.0V meaning a 7V supply is needed to give the required VDDH voltage of 6V. However, the switching node voltage can go as high as +0.5V during forward conduction, meaning that the effective gate driver supply voltage is only 5.5V. If the gate driver supply voltage is too low, the GaN HEMT will not be fully enhanced and the conduction losses will be higher. This condition is especially critical in burst mode or for the initial pulse after turn-on when the bootstrap capacitor may not be fully charged due to the narrow first pulse.



Fig. 4: Typical high-side bootstrap supply circuit showing unwanted parasitic inductances


However it is not advisable to increase the supply voltage to 7.5V to guarantee a minimum 6V VDDH voltage because during reverse conduction conditions, ...

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