Designing Robust Transistor Circuits with IGBTs, SIC MOSFETs
Feb 5, 2019
This whitepaper shares some design guidelines and advice on how to reduce failure causes and simplify the design - with application examples for a better comprehension.
1. Designing Robust Transistor Circuits with IGBTs and SiC MOSFETs
When evaluating new switching transistors circuits, often only the transistor specifications are considered. However, a very significant contributor in the robustness of the final design is the driver circuit. To explore the effect of the driver parameters, let us first consider the ideal conditions using the following example of an IGBT transistor (IKW20N60H3).
From the transistor datasheet, the following conditions prevail at 25°C:
Gate emitter voltage threshold = 4.1V - 5.7V
With these values, a gate driver supply of +15V and GND would be sufficient and the driver circuit would look something like this:
Fig. 1: Simple gate driver circuit for an ideal IGBT
Looks pretty simple! However, when the parasitic elements are considered, the real-life model becomes more complex:
Fig. 2: Realistic gate driver circuit including IGBT parasitic components
If we now take into account that the gate emitter threshold also varies over temperature range, it can be readily seen that the threshold voltage decreases with increasing temperature significantly (several mV / °K) and in the worst case is significantly lower than the typical minimum value of 4.1V as measured at 25°C.
Fig. 3: Gate-Emitter threshold voltage variation with temperature
The driver circuit must be designed to prevent unwanted turn-on in all operating conditions. Otherwise, this can lead to shoot-through short circuits, which can manifest itself in increased losses, increased component stress, shorter service life, worse EMC and in extreme cases to the destruction of the transistor.
Essentially we have two kinds of unwanted switch-on timing:
An unwanted turn-on due to the effect of the Miller capacitance (Creverse)
An unwanted turn-on due to the effect of the parasitic inductances (Lgate and Lemitter).
From the transistor datasheet, the following conditions prevail at 25°C:
Vge max = ± 20V
Gate emitter voltage threshold = 4.1V - 5.7V
With these values, a gate driver supply of +15V and GND would be sufficient and the driver circuit would look something like this:
Fig. 1: Simple gate driver circuit for an ideal IGBT
Looks pretty simple! However, when the parasitic elements are considered, the real-life model becomes more complex:
Fig. 2: Realistic gate driver circuit including IGBT parasitic components
If we now take into account that the gate emitter threshold also varies over temperature range, it can be readily seen that the threshold voltage decreases with increasing temperature significantly (several mV / °K) and in the worst case is significantly lower than the typical minimum value of 4.1V as measured at 25°C.
Fig. 3: Gate-Emitter threshold voltage variation with temperature
The driver circuit must be designed to prevent unwanted turn-on in all operating conditions. Otherwise, this can lead to shoot-through short circuits, which can manifest itself in increased losses, increased component stress, shorter service life, worse EMC and in extreme cases to the destruction of the transistor.
Essentially we have two kinds of unwanted switch-on timing:
An unwanted turn-on due to the effect of the Miller capacitance (Creverse)
An unwanted turn-on due to the effect of the parasitic inductances (Lgate and Lemitter).
2. An unwanted turn-on due to the effect of the Miller capacitance
As the Collector Emitter voltage rises, either when the low-side IGBT is turned off or in a bridge circuit, the high-side IGBT is turned on and current flows the anti-parallel diode, the Miller capacitance, Creverse, must be charged up.
The Miller capacitance charging current can be calculated as follows:
The Miller capacitance is given in most transistor datasheets, but this is, however, just a rough value. The value of Creverse is strongly voltage dependent and also varies with temperature and current. Most datasheets only define the Miller capacitance under certain ideal conditions, so measuring the value under real operating conditions is strongly recommended. The following graph shows the effect of VCE on the reverse capacitance:
Fig. 4: Variation of Creverse with VCE in an IGBT (IKW20N60H3)
The additional capacitive load of Creverse will not be a problem for most driver circuits; it only becomes an issue when the input capacitance CInput also becomes sufficiently charged by the current flowing through Creverse that the transistor turns on again.
The charging current of CInput can be defined from the following ...
The Miller capacitance charging current can be calculated as follows:
Fig. 4: Variation of Creverse with VCE in an IGBT (IKW20N60H3)
The additional capacitive load of Creverse will not be a problem for most driver circuits; it only becomes an issue when the input capacitance CInput also becomes sufficiently charged by the current flowing through Creverse that the transistor turns on again.
The charging current of CInput can be defined from the following ...
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