Chapter 6: Active Components

The metal oxide silicon field effect transistor (MOSFET) is the workhorse of the majority of AC/DC circuits. The basic construction is simple with a gate insulated from the body by a thin metal oxide layer. The source and drain regions are heavily doped (n+ and p+) so that there is a semiconductor barrier to the flow of charge.

When a gate-source voltage higher than the threshold voltage is applied, this barrier is overcome and current flows freely:


Integral to the MOSFET’s construction is a body diode formed from the PN junction between the P+ and N- interface (shown in red in the figure). This means that a MOSFET can only be used to switch unipolar voltages. However, in some applications, the body diode is useful as a freewheeling diode to conduct negative voltages across a MOSFET that is switched off.

The equivalent model shows the various parasitic elements that affect the switching performance:


The turn-on characteristic of a MOSFET can be divided into 4 stages:


The turn-off characteristics is essentially the same process in reverse:


Practical Tip: As can be seen from the turn on and turn off characteristics, there are periods when the voltage across the transistor and the current through the resistor are in transition. One dangerous area is turn off , stage 2. The output voltage is ramping up and this dv/dt will feed back through the miller capacitance and attempt to pull up the gate voltage. If the eff ective gate drive impedance is too high, the transistor can switch itself back on again!

A similar eff ect can occur during switch on, stage 2. The drain current is ramping up which can cause the drain voltage to rise up due to inductances in the drain to ground path (ground bounce). This will reduce the eff ective VGS voltage and could turn the transistor back off again.

See the final section in this chapter (Use of Kelvin contacts) for considerations to reduce or eliminate these effects.

During these stage 2 and stage 3 transition periods, the transistor is behaving as a variable resistor and dissipating a lot of power. When the transistor is fully off, only leakage currents flow and when the transistor is fully on the main loss is through the R_DSON resistance, which is typically in the region of mOhms and also very low. However, during repetitive on-off transitions, the power dissipation will be much higher than in the fully on condition.

A simplified gate drive and switching loss calculation is shown below:


Where Q_gate is the total charge needed to charge the gate capacitances.

The power dissipation in the transistor is dependent on the transition times:


Where I_L is the load current and t_stage2 / t_stage3 is the time spent is stages 2 and 3 of the total switching time, T, respectively.

With a high current gate drive, these stage 2 and stage 3 times can be reduced, so it is important to use a low impedance gate voltage source. To reduce the switching losses further, the gate voltage can be increased to charge and discharge the gate capacitances more quickly. In particular, if the gate voltage switches to a negative value, the switch-off time can be reduced significantly compared to just switching from above VTH down to zero volts. There is a limit to the gate voltage defined by the breakdown voltage between gate and source, BVDSS. In order to reduce the gate capacitance to a minimum, the metal oxide insulation layer is made very thin, at the cost that the breakdown voltage is then very low (V_>GS,max is typically ±15-20 volts).

Another way to reduce switching losses is to reduce the switching frequency, f_sw, but this can increase losses in other parts of the circuit or reduce the response time to unacceptable levels. The only other factor remaining is the gate charge, Q_gate. A typical low voltage MosFET will have a total gate charge of around 5-10nC, but this value also increases with increased V_DS capability. A 700V MosFET will have a total gate charge of around 10-25nC, simply due to the thicker epitaxial layers needed for the higher breakdown voltage strength.

Silicon Carbide or SiC MOSFETs are increasingly finding new applications in power electronics. Full-bridge and half-bridge circuits for high-voltage applications (several hundred volts) were previously reserved for only the IGBT domain (see next section) because Silicon MOSFETs, especially Super Junction MOSFETs are not suitable for these applications due to the extremely poor parasitic body diode performance; when silicon MOSFETs experience an unwanted turn-on effect, the body diode quickly goes into thermal destruction. Often, even a single false switching operation on the conductive body diode either exceeds the maximum dI/dt of the body diode and thus destroys the FET, or the switching operation incites the gate to oscillate, so that the maximum gate source voltage is exceeded and transistor is also destroyed.

SiC FETs use a different substrate with a 10x higher dielectric breakdown strength than Silicon, so the layers can be made thinner to reduce the gate charge and R_DSon values. In addition, SiC has a three times better thermal conductivity, so the power handling capacity can be increased in the same sized package.


Due to the higher dielectric strength, the SiC substrate can be made up to 10x thinner than the Si Substrate, reducing the body resistance by a factor of up to 1:1000. The thinner layers also reduce the internal capacitances. So, for the same switching frequency, a SiC MOSFET will have around a third to a quarter of the switching losses of an equivalent Si MOSFET. Put another way, a SiC MOSFET can be operated four times faster for the same power dissipation.

SiC MOSFETs also have a far more robust body diode than Si MOSFETS. The maximum switching dI/dt of the body diode of super junction MOSFETs is around 60Aμs^-1 for the latest generation of fast switching MOSFETs up to 900Aμs-1 for SJ MOSFETs with ultra-fast body diodes, but these values pale in comparison with SIC MOSFETs with up to 6000Aμs^-1. The main disadvantage of SiC-MOSFETs is that they are often more expensive than Si-MOSFETs, but this difference will reduce over time (the price difference between a SiC-MOSFET and a superjunction Si-MOSFET is already comparable).

Insulated gate bipolar transistors combine the insulated gate characteristics of MOSFETs with the high current capability of bipolar transistors. It is in effect a voltage controlled transistor:


One of the main differences to a MOSFET is that an IGBT has no body diode, so it will not conduct reverse currents. If an anti-parallel free-wheeling diode is required, then it needs to be added externally.




Despite this disadvantage, IGBTs are widely used in power switching for high current / high voltage applications such as motor inverters, power rectifi ers and photovoltaic power.

Gallium Nitride (GaN) semiconductors are High Electron Mobility Transistor (HEMT) devices, a class of transistors with almost perfect switching characteristics. HEMT means that electrons travel within the internal crystal structure as a two dimensional electron gas with very high mobility, thus creating a device with very high conductivity and low R_DSON. The use of GaN chemistry increases the breakdown voltage which means that the layers within the transistor can be made very thin and close together. This both accelerates the switching speed and reduces the gate capacitance.

The enhancement mode type (E-HEMT) has a depletion zone under the gate which blocks the fl ow of electrons and requires a positive gate voltage with respect to the source pin to turn on. As the depletion zone under the gate is so thin, very little injected charge is needed to turn the transistor on and off , so switching speeds in the MHz region are possible without incurring high switching losses.


The extreme thinness of the gate isolation layer means that high gate-source voltages will cause an internal flashover, even though the material itself has a high breakdown voltage rating. A GaN E-HEMT has a typical full enhancement voltage of 7V but will be damaged if the VGS exceeds ±10V, much lower than the gate voltages that are typically used in IGBT or SiC gate drivers. Due to the extremely fast rise and fall times of the low-capacitance gate channel, any excessive inductance in the external gate drive could cause spikes or voltage ringing and exceed these voltage limits. Therefore a 6V gate drive voltage is a good compromise between high efficiency and staying within a safe operating area.

IGBT or SiC gate drive circuits also typically turn off with a negative gate drive voltage. This speeds up the charge extraction from the gate capacitance and therefore the switch-off time. GaN Transistors have such low gate capacitance that a negative gate drive is not necessary. A gate voltage of 0V will completely and reliably turn off the HEMT in nanoseconds.

Only if the layout has excessive inductance would a negative gate drive offer protection against unintentional turn-on caused by ringing. However, as HEMT do not have a body diode like a MOSFETs and are symmetrically conductive devices, a negative gate voltage will increase reverse conduction losses. A single ended 6V gate drive voltage is sufficient, although for very high frequency switching applications, a bipolar +6V/-1V is sometimes suggested to account for layout parasitics.

Figure 11 shows typical gate driver voltages that are commonly used to drive the switching transistors. The 1st Generation SiC MOSFETS use +20/-5V supplies, but 2nd Generation devices will use +15/-3V supply voltages:

1. The majority of ultrafast gate drivers ICs have an under-voltage lock-out (UVLO) function that disables the output if the supply voltage is too low. Those meant for IGBT/SiC applications will often have a relatively high UVLO level as they are designed to operate from supply voltages up to 24V. A gate driver that is compatible with the much lower gate voltages used in GaN must be selected.


2. The current needed to charge and discharge the gate capacitance is dependent on the gate capacitance and the rate of change of the gate voltage. Although the GaN gate capacitance is very low, the high dv/dt means that a gate driver with a current drive capability of at least ±0.5A (or better 1A sink) is required. This peak current will be supplied from a ceramic capacitor mounted as close to the driver pins as possible, so the average supply current will be much lower (in the tens of milliamps range). The gate driver sink drive should be low-impedance (<2 Ohms) to reduce the chance of cross-conduction (see next comment).


3. The maximum and minimum pulse widths should be limited to avoid false triggering and interaction with the overlap protection circuit. At 5 MHz operating frequency, this minimum pulse width limits the duty cycle to 90%. At higher frequencies, this limitation becomes more significant and the duty cycle may need to be controlled so that it does not exceed 80%.


4. An ultrafast gate drive design is susceptible to undesired turn-on (cross-conduction) due to parasitic gate driver inductances interacting with the high Miller capacitance discharge current thus creating a ringing oscillation that could send the gate voltage momentarily high again. The slew rates can be limited by a dv/dt limiting resistor to reduce the possibility of this effect.

A turn-on gate resistor in the range of 10-20 Ohms will typically give an 80-40kV/μs slew rate. The turn-off resistance should be smaller to reduce the turn-off losses. A Schottky diode with a resistor in parallel with the gate resistor can be used to independently control the turn-on and turn-off slew rates:




Fig. 12: Slope control using gate resistors


5. High side gate drivers are often implemented with a bootstrap power supply circuit (figure 13) Although this means that the same isolated power supply can be used for both highside and low-side drivers, it has some inherent weaknesses.





Fig. 13: Typical high-side bootstrap supply circuit showing unwanted parasitic inductances. For a nominal 6V VDDH, the bootstap voltage can vary between 5.5V and 8.5V depending on operating conditions (see text below).

The bootstrap diode must have an ultrafast recovery characteristic. If it cannot switch as quickly as the GaN output then a reverse current will flow back into the VDD supply. Not only will these current spikes affect the lifetime of the diode but the resulting high frequency interference on the supply rail will cause havoc with the EMC compliance. The gate driver bootstrap supply voltage is dependent on the difference between the VDD supply and the capacitively-coupled output (switching node) voltage. This means that the voltage across the bootstrap capacitor can vary by more than ±20% during operation.

There will be a volt drop across the bootstrap diode of around 0.7V meaning a 6.7V VDD would be needed to have a VDDH voltage of 6V. The switching node voltage may not go completely to the ground voltage during forward conduction, meaning that the effective gate driver supply voltage may be as low as 5.5V. If the gate driver supply voltage is too low, the GaN HEMT will not be fully enhanced and the conduction losses will be higher.

However it is not advisable to increase the VDD supply voltage because during reverse conduction conditions, the switching node voltage can swing to as much as -2.5V below ground, meaning an effective bootstrap voltage is +6.7V -0.7V +2.5V = 8.5V. This is getting perilously close to the absolute maximum gate voltage of 10V. In addition, the interaction with the load current and parasitic inductances can cause negative-going spikes to be generated at the switching node by high di/dt transitions. There could be operating conditions where the bootstrap voltage will exceed 10V when the di/dt undershoot spikes are also taken into account.

A more reliable solution is to use a separate galvanically isolated supply for the high-side gate driver. This will ensure a stable gate voltage swing irrespective of the operating conditions.


6. Gate driver inductances can be minimized by good design, but it is more difficult to control the parasitic inductances of the power ground as the layout choices for high current paths are more restricted. Although a low-side switching circuit has common power ground and gate driver ground, any parasitic layout inductances will create ground bounce under high di/dt conditions. For operational safety, it is therefore advisable also to galvanically isolate the low-side drivers as well as the high-side drivers. If the gate drivers are isolated, then the influence of the layout power ground inductances can be eliminated by connecting the gate driver ground directly to the transistor source connection (or to the Kelvin connection if this is supported in the transistor package).



7. The PWM isolator and galvanically isolated DC/DC converter should have low isolation capacitance. The high dv/dt slew rates and switching frequencies possible with GaN devices will stress the isolation barrier, even if the absolute voltage swings are well within the voltage ratings of the components. For high dv/dt applications, the isolation capacitance should be <4pF for the PWM isolator and <10pF for the high side DC/DC converter. If a DC/ DC converter is also used on the low side to eliminate ground bounce, then the isolation capacitance is not so critical, however an isolation capacitance of <100pF is desirable.

Practical Tip: Isolated GaN Power Switch.


This floating design uses an isolated DC/DC converter and digital isolator to create a gate driver circuit for a GaN HEMT that could be used as a boost converter, buck converter or buck/boost converter switching application on either the high side or low side. The single-channel digital isolator output stage is powered from a low power LDO regulator connected to the 6V gate driver supply. The UCC27322 high speed driver can deliver up to ±9A peak current and the Schmitt-trigger input switches cleanly from the 5V output of the digital isolator. A deadtime delay can be implemented with a simple RC filter.

The lateral construction of GaN transistors also creates the possibility to integrate the gate driver inside the transistor package. This reduces the parasitic gate inductances and allows higher switching frequencies or higher slew rates without the risk of false triggering. Nevertheless, an isolated gate driver power supply and drive signal isolator are still required.

Irrespective of the power transistor type used (see table below), a careful PCB layout is required when switching high voltages and high currents.


The following discussion is based on IGBT switching transistors, but the basic principles are the same for Si-MosFETS, SiC-MosFETS and GaN-MOSFETs.


The driver circuit must be designed to prevent unwanted turn-on in all operating conditions. Otherwise, this can lead to shoot-through short circuits, which can manifest itself in increased losses, increased component stress, shorter service life, worse EMC and in extreme cases, to the destruction of the transistor.

Essentially we have 2 kinds of unwanted switch-on timing:

• An unwanted turn-on due to the eff ect of the CGE capacitance (C_reverse).
• An unwanted turn-on due to the eff ect of the parasitic inductances (L_gate and L_emitter)

As the Collector Emitter voltage rises, either when the low-side IGBT is turned off or in a bridge circuit, the high-side IGBT is turned on and current fl ows through the anti-parallel diode, the Miller capacitance, Creverse, must be charged up. The Miller capacitance charging current can be calculated as follows:


The Miller capacitance is given in most transistor datasheets, but this is, however, just a rough value. The value of C_reverse is strongly voltage dependent and also varies with temperature and current. Most data sheets only defi ne the Miller capacitance under certain ideal conditions, so measuring the value under real operating conditions is strongly recommended.

The following graph shows the eff ect of VCE on the reverse capacitance:


The additional capacitive load of C_reverse will not be a problem for most driver circuits; it only becomes an issue when the Gate-Emitter capacitance C_input becomes sufficiently charged by the remaining current flowing from Creverse that the gate voltage can rise so that transistor turns on again.

The charging current of C_input can be defined from the following relationship:


Where Idriver is dependent on the gate driver internal impedance, the DC gate resistance and the AC impedance of L_gate.


So what measures can be taken to avoid undesired turn-on due to the reverse capacitance current?

1. Limit the dV/dt. By slowing the rate of change of the V_CE voltage, the C_reverse current is reduced. However, this means higher switching losses.
2. Reduce the parasitic inductance L_gate. By suitable choice of layout and package, the C_reverse current can be diverted away from charging up the gate-emitter capacitance, C_input. However, this restricts the design freedom of the PCB layouter.
3. Use a negative gate emitter voltage. If the driver output goes negative, the gate is held hard off and the safety distance between the gate turn-on threshold voltage and actual gate voltage is increased. Thus an unwanted turn-on is impossible even under worst case dv/dt conditions.
4. Use GaN HEMTs which have a negligible reverse capacitance.

In the ON state, current flows through the transistor and also through the emitter-side inductance of the load current. If the current is now turned abruptly off, a negative voltage is generated by emitter-side load inductance voltage according to the following relationship:


Even a short 3cm PCB track can have an inductance of a few microhenries. A via will have an inductance of tens of microhenries. This does not sound much, but at very high current slew rates the resulting voltage drop can be in the order of volts. The voltage at the emitter is thus significantly lower than the Powerground reference. If the gate driver output ground reference is at the same Powergnd potential, this results in a positive gate-emitter voltage and if this voltage exceeds the threshold voltage, the transistor will then momentarily switch on again.

In bridge arrangements, the inductances of the other bridge branches and the PCB layout can add to the effective emitter-side load inductance.


Non-isolated gate driver circuits in bridge arrangements can often exhibit significant potential differences between of the various connection points of Powergnd and the gate driver grounds, thereby leading to a significant impact on potentially unwanted turn-on effects due to the parasitic inductances. In order to reduce the ground potential differences, it is necessary to connect the system ground to point Powergnd2 and also to use a star-earth connection to driver ground connections, GND-Driver. Furthermore, the inductance L_Layout must be nearly the same on both sides of the bridge.

Often the layout does not allow for absolute symmetry. If the system Powergnd is now connected to the point Powergnd1 instead of Powergnd2, then the right-hand branch will exhibit an increased gate-emitter voltage equal to:


The same imbalance is true if the system Powergnd is connected closer to the point Powergnd2 for the left-hand branch, of course.

Practical Tip: How do you to check whether your gate driver design is safely under the gate emitter threshold voltage during operational switching operations?

It is not as simple as just attaching an oscilloscope probe and monitoring the gate voltage as direct access to the gate and emitter is difficult in practice and the readings will be affected by the capacitance loading of the probe itself. Thus, the measured values do not necessarily reflect reality. (Wer Mist misst, misst Mist: Who wrongly measures, measures wrongly).

Rather, you need to measure the inductances L_emitter, L_gate and in some cases even L_Layout and do the necessary calculations.

One way to find out if there are momentary unwanted turn-on effects in a bridge design is to measure the current in each branch of the bridge. Again, one must be careful that you do not change the switching behaviour of IGBTs by measuring the current. Thus, there must be no additional resistances or inductances in the gate-emitter path. One method which has been proven to be reasonably accurate is to use a current shunt in the high side collector connection and an isolated oscilloscope as shown below:


Even if this measurement does not reveal any unwanted current peaks, you still cannot assume that the design is safe under all operating conditions. To be sure, you would have to have to select transistors having the minimum threshold voltages given in the datasheet and test at the maximum permissible temperature and maximum dI/dt and dv/dt levels. So what can be done to minimize the unwanted effects of parasitic inductances?

1. Reduce dI/dt. Slower current decay rates result in lower voltages induced in the parasitic inductances and thus lower voltages between gate and emitter. However, this increases the switching losses.
2. Reduce the layout inductance. The lower the layout inductance (track or cable lengths), the smaller the parasitic voltage generated.
3. Use negative gate emitter voltages. By using a negative gate-emitter voltage instead of GND, the safety distance of the gate-emitter voltage to the gate emitter threshold voltage is increased.
4. Galvanically separate the gate drive from the power ground. Through the use of isolated gate drivers for each transistor, the influences of the emitter inductances can be eliminated as the driver supply ground point is connected directly to the respective transistor emitters. Now that the L_emmiter parasitics are not part of the driver current loop, their effect is eliminated.
   
   
   
   Fig. 20: Isolated low side gate drivers.
5. Use Kelvin contacts.

Several transistor manufacturers now offer packages in which a separate kelvin connection is provided for the emitter. Although this also has its own small parasitic inductance due to the connection path, the main load current does not flow through it, so no induced voltage is generated by any load current variations. This solution eliminates the effects of both the L_emitter and L_layout parasitic inductances.


In summary: there are many ways to prevent undesired turn-on of a power transistor, but there are, however, just as many dangers that it happens! The safest way to prevent unwanted turn-on switching is to use an isolated dual supply for the gate driver with a negative turn-off voltage and to keep the parasitic inductances as low as possible. Ideally, a transistor package with Kelvin connections should be used to eliminate the effect of layout inductances.

RECOM has developed an evaluation board (R-REF01-HB) to allow circuit designers to experiment and compare the different IGBT, SiC and GaN switching technologies using the same layout and driver IC. Only the DC/DC converters (included) need to be selected to match the transistors being used. The layout can be used for both three pin and four pin transistors with Kelvin contact.