DC/DC Converters for GaN Gate Drivers
Feb 5, 2019
This whitepaper shows how the usage of DC/DC converters with low leakage capacitance and compliance with design guidelines eliminate these causes of failure and simplify the design.
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GaN Gate Drive Considerations - lntroduction
Gallium Nitride (GaN) semiconductors are High Electron Mobility Transistor (HEMT) devices—a class of transistors known for their near-ideal switching characteristics. In a HEMT, electrons move within the crystal structure as a two-dimensional electron gas with extremely high mobility, resulting in a device with excellent conductivity and low RDS(ON). The unique properties of GaN increase the breakdown voltage, allowing the internal transistor layers to be made thinner and more closely spaced. This enhances switching speed and lowers gate capacitance.
Enhancement-mode GaN transistors (E-HEMTs) feature a depletion zone beneath the gate that blocks electron flow until a positive gate voltage is applied relative to the source pin. Because this depletion zone is extremely thin, only a small amount of charge is required to turn the device on or off, enabling switching speeds in the MHz range without significant switching losses.
Fig. 1: Diagrammatic layout of an Enhancement Mode GaN Transistor in the OFF and ON modes
The extreme thinness of the gate isolation layer means that high gate-source voltages can cause internal flashover, despite the material’s high breakdown voltage rating. A GaN E-HEMT typically reaches full enhancement at 7V but can be damaged if VGS exceeds ±10V — significantly lower than the gate voltages commonly used in IGBT or SiC gate drivers. Due to the very fast rise and fall times of the low-capacitance gate channel, any excessive inductance in the external gate drive may cause voltage spikes or ringing, potentially exceeding these voltage limits. A 6V gate drive voltage provides a good balance between efficiency and safe operation.
IGBT and SiC gate drive circuits often use a negative gate voltage during turn-off to accelerate charge extraction from the gate capacitance, reducing switch-off time. In contrast, GaN transistors have such low gate capacitance that a negative gate voltage is unnecessary. A 0V gate voltage will reliably turn off the HEMT in nanoseconds. Only in cases of excessive layout inductance would a negative gate drive offer protection against unintended turn-on from ringing. However, since HEMTs lack a body diode like MOSFETs and conduct symmetrically, a negative gate voltage increases reverse conduction losses. A single-ended 6V–0V gate drive is ideal. Figure 2 illustrates typical gate driver voltages used for GaN, along with those for IGBT and first- and second-generation SiC devices.
Fig. 2: Typical Gate Driver supply voltages for IGBT, SiC and GaN drivers
Enhancement-mode GaN transistors (E-HEMTs) feature a depletion zone beneath the gate that blocks electron flow until a positive gate voltage is applied relative to the source pin. Because this depletion zone is extremely thin, only a small amount of charge is required to turn the device on or off, enabling switching speeds in the MHz range without significant switching losses.
Fig. 1: Diagrammatic layout of an Enhancement Mode GaN Transistor in the OFF and ON modes
The extreme thinness of the gate isolation layer means that high gate-source voltages can cause internal flashover, despite the material’s high breakdown voltage rating. A GaN E-HEMT typically reaches full enhancement at 7V but can be damaged if VGS exceeds ±10V — significantly lower than the gate voltages commonly used in IGBT or SiC gate drivers. Due to the very fast rise and fall times of the low-capacitance gate channel, any excessive inductance in the external gate drive may cause voltage spikes or ringing, potentially exceeding these voltage limits. A 6V gate drive voltage provides a good balance between efficiency and safe operation.
IGBT and SiC gate drive circuits often use a negative gate voltage during turn-off to accelerate charge extraction from the gate capacitance, reducing switch-off time. In contrast, GaN transistors have such low gate capacitance that a negative gate voltage is unnecessary. A 0V gate voltage will reliably turn off the HEMT in nanoseconds. Only in cases of excessive layout inductance would a negative gate drive offer protection against unintended turn-on from ringing. However, since HEMTs lack a body diode like MOSFETs and conduct symmetrically, a negative gate voltage increases reverse conduction losses. A single-ended 6V–0V gate drive is ideal. Figure 2 illustrates typical gate driver voltages used for GaN, along with those for IGBT and first- and second-generation SiC devices.
Fig. 2: Typical Gate Driver supply voltages for IGBT, SiC and GaN drivers
GaN Gate Drive Considerations - Design Guidelines
Fig. 3: Slope control using gate resistors
- Most ultrafast gate driver ICs include an under-voltage lockout (UVLO) function that disables the output when the supply voltage is too low. Gate drivers designed for IGBT or SiC applications often feature relatively high UVLO thresholds, as they are intended to operate from supply voltages up to 24V. For GaN applications, a gate driver compatible with significantly lower gate voltages must be selected.
- The current required to charge and discharge the gate is determined by both the gate capacitance and the rate of voltage change. Although GaN gate capacitance is relatively low, the high dv/dt necessitates a gate driver capable of supplying at least ±0.5A—ideally 1A for sink current. This peak current should be delivered from a ceramic capacitor placed as close as possible to the driver pins. The average supply current, however, remains low — typically in the tens of milliamps. The gate driver sink path should have a low impedance (<2 Ohms) to minimize the risk of cross-conduction.
- Ultrafast gate drive designs are prone to unintended turn-on (cross-conduction), caused by parasitic gate driver inductances interacting with the Miller capacitance discharge current. This can result in ringing that briefly elevates the gate voltage. To mitigate this, the slew rate should be limited using a dv/dt limiting resistor. A turn-on gate resistor in the 10–20 Ohm range typically yields an 80–40kV/µs slew rate. To minimize turn-off losses, the turn-off resistance should be lower. A Schottky diode in parallel with a gate resistor allows independent control of turn-on and turn-off slew rates in a single-output driver (see Figure 3).
- High-side gate drivers are often implemented using a bootstrap power supply circuit (Figure 4). While this allows the same isolated power supply to be shared between both high-side and low-side drivers, the approach has several inherent limitations.
The bootstrap diode must have an ultrafast recovery characteristic. If it cannot turn off as quickly as the GaN switch, reverse current will flow back into the VDD supply. These current spikes not only reduce the diode’s lifespan but also introduce high-frequency interference on the supply rail, severely impacting EMI compliance.
The gate driver’s bootstrap supply voltage depends on the difference between the VDD supply and the capacitively-coupled output (switching node) voltage. As a result, the voltage across the bootstrap capacitor can fluctuate by more than ±20% during operation.
There is a voltage drop of approximately 0.8–1.0V across the high-voltage bootstrap diode, requiring a 7V supply to achieve the desired VDDH voltage of 6V. However, during forward conduction, the switching node voltage can rise to +0.5V, reducing the effective gate driver supply voltage to just 5.5V. If this voltage is too low, the GaN HEMT will not be fully enhanced, leading to increased conduction losses. This issue is particularly critical in burst mode or during the initial pulse after turn-on, when the bootstrap capacitor may not be fully charged due to the narrow pulse width.
Increasing the supply voltage to 7.5V to ensure a minimum VDDH of 6V is not recommended. Under reverse conduction conditions, the switching node can dip as much as -2.5V below ground, resulting in an effective bootstrap voltage of 6.5V + 2.5V = 9V—uncomfortably close to the absolute maximum gate voltage of 10V. Furthermore, interaction between load current and parasitic inductances can produce negative-going spikes at the switching node during high di/dt transitions. These transients may push the bootstrap voltage above 10V, posing a risk of gate overvoltage.
Fig. 4: Typical high-side bootstrap supply circuit showing unwanted parasitic inductances
A more reliable solution is to use a dedicated galvanically isolated supply for the high-side gate driver. This approach ensures ...
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